.. _CIM-PCIBridge: CIM_PCIBridge ------------- Class reference =============== Subclass of :ref:`CIM_PCIDevice ` Capabilities and management of a PCI controller that provide bridge-to-bridge capability. Key properties ^^^^^^^^^^^^^^ | :ref:`SystemName ` | :ref:`DeviceID ` | :ref:`CreationClassName ` | :ref:`SystemCreationClassName ` Local properties ^^^^^^^^^^^^^^^^ .. _CIM-PCIBridge-MemoryBase: ``uint16`` **MemoryBase** Base address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0. .. _CIM-PCIBridge-IOLimit: ``uint8`` **IOLimit** End address of the I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 1. .. _CIM-PCIBridge-IOBase: ``uint8`` **IOBase** Base address of I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 0. .. _CIM-PCIBridge-IOBaseUpper16: ``uint16`` **IOBaseUpper16** Upper 16 bits of the supported I/O base address when 32-bit I/O addressing is used. The lower 16 bits are assumed to be 0. .. _CIM-PCIBridge-PrefetchLimitUpper32: ``uint32`` **PrefetchLimitUpper32** Upper 32 bits of the supported prefetch end address when 64-bit addressing is used. The lower 32 bits are each assumed to be 1. .. _CIM-PCIBridge-BridgeType: ``uint16`` **BridgeType** The type of bridge. Except for "Host" (value=0) and "PCIe-to-PCI" (value=10), the type of bridge is PCI-to-. For type "Host", the device is a Host-to-PCI bridge. For type "PCIe-to-PCI", the device is a PCI Express-to-PCI bridge. ======== ============= ValueMap Values ======== ============= 0 Host 1 ISA 2 EISA 3 Micro Channel 4 PCI 5 PCMCIA 6 NuBus 7 CardBus 8 RACEway 9 AGP 10 PCIe 11 PCIe-to-PCI 128 Other .. DMTF Reserved ======== ============= .. _CIM-PCIBridge-SecondaryBusDeviceSelectTiming: ``uint16`` **SecondaryBusDeviceSelectTiming** The slowest device-select timing for a target device on the secondary bus. ======== ============= ValueMap Values ======== ============= 0 Unknown 1 Other 2 Fast 3 Medium 4 Slow 5 DMTF Reserved ======== ============= .. _CIM-PCIBridge-SecondayBusNumber: ``uint8`` **SecondayBusNumber** The number of the PCI bus segment to which the secondary interface of the bridge is connected. .. _CIM-PCIBridge-SecondaryStatusRegister: ``uint16`` **SecondaryStatusRegister** The contents of the SecondaryStatusRegister of the Bridge. For more information on the contents of this register, refer to the PCI-to-PCI Bridge Architecture Specification. .. _CIM-PCIBridge-PrefetchMemoryBase: ``uint16`` **PrefetchMemoryBase** Base address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0. .. _CIM-PCIBridge-PrimaryBusNumber: ``uint8`` **PrimaryBusNumber** The number of the PCI bus segment to which the primary interface of the bridge is connected. .. _CIM-PCIBridge-IOLimitUpper16: ``uint16`` **IOLimitUpper16** Upper 16 bits of the supported I/O end address when 32-bit I/O addressing is used. The lower 16 bits are each assumed to be 1. .. _CIM-PCIBridge-SecondaryLatencyTimer: ``uint8`` **SecondaryLatencyTimer** The timeslice for the secondary interface when the bridge is acting as an initiator. A 0 value indicates no requirement. .. _CIM-PCIBridge-PrefetchMemoryLimit: ``uint16`` **PrefetchMemoryLimit** End address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1. .. _CIM-PCIBridge-SubordinateBusNumber: ``uint8`` **SubordinateBusNumber** The number of the highest numbered bus that exists behind the bridge. .. _CIM-PCIBridge-MemoryLimit: ``uint16`` **MemoryLimit** End address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1. .. _CIM-PCIBridge-PrefetchBaseUpper32: ``uint32`` **PrefetchBaseUpper32** Upper 32 bits of the supported prefetch base address when 64-bit addressing is used. The lower 32 bits are assumed to be 0. Local methods ^^^^^^^^^^^^^ *None* Inherited properties ^^^^^^^^^^^^^^^^^^^^ | ``uint16`` :ref:`VendorID ` | ``uint16`` :ref:`PCIDeviceID ` | ``uint16`` :ref:`RequestedState ` | ``boolean`` :ref:`PowerManagementSupported ` | ``datetime`` :ref:`TimeOfLastStateChange ` | ``uint16[]`` :ref:`Capabilities ` | ``boolean`` :ref:`SelfTestEnabled ` | ``string`` :ref:`SystemName ` | ``string`` :ref:`Description ` | ``uint16`` :ref:`Availability ` | ``string`` :ref:`Status ` | ``string`` :ref:`ElementName ` | ``uint32`` :ref:`ExpansionROMBaseAddress ` | ``string[]`` :ref:`StatusDescriptions ` | ``datetime`` :ref:`InstallDate ` | ``uint16`` :ref:`HealthState ` | ``uint8`` :ref:`DeviceNumber ` | ``uint8`` :ref:`RevisionID ` | ``uint64`` :ref:`Generation ` | ``uint8`` :ref:`LatencyTimer ` | ``uint16`` :ref:`PrimaryStatus ` | ``string`` :ref:`InstanceID ` | ``uint16[]`` :ref:`OperationalStatus ` | ``uint16`` :ref:`SubsystemVendorID ` | ``uint16`` :ref:`DeviceSelectTiming ` | ``uint16`` :ref:`OperatingStatus ` | ``uint16`` :ref:`CommunicationStatus ` | ``uint8`` :ref:`FunctionNumber ` | ``uint16`` :ref:`DetailedStatus ` | ``string[]`` :ref:`OtherIdentifyingInfo ` | ``string`` :ref:`OtherEnabledState ` | ``uint8`` :ref:`MaxLatency ` | ``uint16`` :ref:`EnabledDefault ` | ``uint16`` :ref:`EnabledState ` | ``uint16[]`` :ref:`AdditionalAvailability ` | ``string`` :ref:`Caption ` | ``uint16`` :ref:`InterruptPin ` | ``uint16`` :ref:`CommandRegister ` | ``uint16`` :ref:`StatusInfo ` | ``string[]`` :ref:`CapabilityDescriptions ` | ``datetime`` :ref:`TimeOfLastReset ` | ``uint16[]`` :ref:`PowerManagementCapabilities ` | ``uint32`` :ref:`MaxNumberControlled ` | ``uint16`` :ref:`SubsystemID ` | ``uint64`` :ref:`PowerOnHours ` | ``uint16`` :ref:`TransitioningToState ` | ``uint16[]`` :ref:`AvailableRequestedStates ` | ``uint8`` :ref:`CacheLineSize ` | ``uint16`` :ref:`ProtocolSupported ` | ``uint8`` :ref:`BusNumber ` | ``uint64`` :ref:`MaxQuiesceTime ` | ``uint64`` :ref:`TotalPowerOnHours ` | ``uint8`` :ref:`ClassCode ` | ``string`` :ref:`ErrorDescription ` | ``string`` :ref:`ProtocolDescription ` | ``uint64[]`` :ref:`BaseAddress64 ` | ``string[]`` :ref:`IdentifyingDescriptions ` | ``uint16`` :ref:`LocationIndicator ` | ``boolean`` :ref:`ErrorCleared ` | ``uint32`` :ref:`LastErrorCode ` | ``string`` :ref:`SystemCreationClassName ` | ``string`` :ref:`Name ` | ``string`` :ref:`CreationClassName ` | ``uint32[]`` :ref:`BaseAddress ` | ``uint8`` :ref:`MinGrantTime ` | ``string`` :ref:`DeviceID ` Inherited methods ^^^^^^^^^^^^^^^^^ | :ref:`Reset ` | :ref:`RequestStateChange ` | :ref:`SetPowerState ` | :ref:`QuiesceDevice ` | :ref:`BISTExecution ` | :ref:`EnableDevice ` | :ref:`OnlineDevice ` | :ref:`SaveProperties ` | :ref:`RestoreProperties `